module top;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
number n1(e,a,b,c,d);
endmodule
module number(e,a,b,c,d);
input a,b,c,d;
output e;
wire a1,b1,c1,d1,w1,w2,w3,w4;
nand(a1,a);
nand(b1,b);
nand(c1,c);
nand(d1,d);
nand(w1,c,d);
nand(w2,a1,b1,c);
nand(w3,a,b,d);
nand(w4,a,b1,c);

nand(e,w1,w2,w3,w4);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule